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  • Support for all codes defined in 5G NR standard (3GPP TS 38.212)

  • ​Coded throughput up to 68Gb/S for ASIC and 18.5Gb/s for FPGA

  • Easily customizable as per request by the customer

  • Provide separate optimized designs for filler bit insertion at the input and  puncturing and filler bit removal at the output.

For FPGA: 

Clock frequency at 270MHz

Coded throughput up to 18.5Gb/s

Latency : < 1.384us

Flop counts : 6381

LUT : 14k

BRAM : 5.5

For ASIC*:

Clock frequency at 1GHz

Coded throughput up to 68Gb/s

Latency : < 0.374us

Flop count: 7000

SRAM : 3.19KB​

​*Note: the above data are estimated.

This high-quality LDPC Encoder is for sale. Please contact us.

Contact Us

​​​Worldwide Headquarters (USA)

AmRidge Technologies LLC

101 Summit Dr. 
Basking Ridge, NJ 07920 USA
Tel: +1-908-655-8783

jjia@amridgetech.com

Technical Support:

jerome.jia@gmail.com

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